1. Technical Field
The embodiments described herein relate to a semiconductor integrated apparatus, and more particularly, to a semiconductor integrated apparatus comprising a fuse circuit that occupies a reduced area.
2. Related Art
In general, even a defect in a single memory cell of a semiconductor apparatus comprising a large number of minute cells can result in operational errors. Therefore, a repair process for substituting a defective cell with a normal memory cell should be performed.
In order to perform such a repair process, a semiconductor integrated apparatus includes a repair circuit, which is provided with a fuse circuit that can be used to determine whether a memory cell is a defective cell or a normal cell. The fuse circuit includes a plurality of fuses, and stores address information related to defective cells according to the connection states of the fuses.
When receiving an external address, the semiconductor integrated apparatus compares the external address with the defective cell address information stored in the fuse box. If the external address and the defective fuse address information correspond to each other, then a defective cell is being addressed and will be substituted with another normal cell.
In order to substitute out a defective cell, repair fuses are disposed in a, e.g., Dynamic Random Access Memory (DRAM). A conventional repair fuse circuit is shown in FIG. 2. As can be seen, this particular circuit has a four-column structure.
A schematic diagram if a conventional fuse circuit 200 is shown in FIG. 1. As can be seen, circuit 200 includes first to sixteenth fuses F0 to F15, first to sixteenth NMOS transistors N1 to N16, a first connection fuse C1, a second connection fuse C2, and a column repair address circuit 10.
One end of each of the first to eighth fuses F0 to F7 is connected in common to a first node Node_1 and the other ends thereof are connected to the first to eighth NMOS transistors N1 to N8, respectively.
One end of each of the ninth to sixteenth fuses F8 to F15 are connected in common to a second node Node_2 and the other ends thereof are connected to the ninth to sixteenth NMOS transistors N9 to N16, respectively.
The fuses F0 to F15 correspond to a plurality of mats and the fuse circuit 200 is configured so that, when failure occurs in a mat, a fuse corresponding to the mat is cut.
The first connection fuse C1 has one end connected to the first node Node_1 and the other end connected to a third node Node_3. The second connection fuse C2 has one end connected to the second node Node_2 and the other end connected to the third node Node_3.
The first to sixteenth NMOS transistors N1 to N16 are connected in series to corresponding fuses, respectively, and receive mat selection signals ‘XMAT_YF<0:15>’ through gates thereof. The mat selection signals ‘XMAT_YF<0:15>’ may be enabled as the corresponding cell mats are selected.
The column repair address circuit 10 generates a column repair address signal according to the voltage on the third node Node_3.
If a fuse corresponding to a selected mat is cut, the column repair address signal is output at a high level. This represents that the selected mat has been repaired by a repair cell mat. For example, if the second fuse F1 has been cut when the second mat selection signal ‘XMAT_YF<1>’ is enabled, the column repair address signal transitions to a high level. Therefore, it can be seen that the second cell mat has been repaired.
Referring again to FIG. 2, a semiconductor integrated apparatus 1 may include a plurality of blocks, and each block may include first to sixteenth fuses F0 to F15, a first connection fuse C1, a second connection fuse C2, and two dummy fuses D1 and D2. As mentioned above, the fuse circuit of each block has a four-column structure, and a plurality of fuses each of which is disposed in the individual columns according to a predetermined pattern. For example, the first to fourth fuses F0 to F3 and the dummy fuse D1 are disposed in the first column. The fifth to eighth fuses F4 to F7 and the first connection fuse C1 are disposed in the second column. The ninth to twelfth fuses F8 to F11 and the second connection fuse C2 are disposed in the third column. The thirteenth to sixteenth fuses F12 to F15 and the dummy fuse D2 are disposed in the fourth column.
The first connection fuse C1 is connected to the second connection fuse C2 so as to connect the first to eighth fuses F0 to F7 to the ninth to sixteenth fuses F8 to F15.
In each fuse circuit, five fuses are disposed at predetermined intervals and the individual columns have the same area. The fuse circuit includes two dummy fuses disposed between fuses for direct connection and symmetry between four columns. As a result, the area of the fuse circuit increases. In other words, while the dummy fuses provide a symmetrical structure; the dummy fuses cause an unnecessary increase in area, which hinders the level of integration that can be achieved.